Huawei Accelerates Ascend 960 AI Chip Launch Amid System-Level Push

Huawei is advancing the launch of its next-generation Ascend 960 series of AI chips, citing faster-than-expected research and development progress. The announcement, made at the company's 2026 Connect conference, signals a significant step in the evolution of China's domestic AI hardware capabilities.

Accelerated Chip Roadmap

According to a research note from CITIC Securities citing conference reports, Huawei has updated the release schedule for its upcoming high-performance chips. The new timeline indicates a substantial acceleration over previous plans.

• The Ascend 960DT is now scheduled for release in Q1 2027, three quarters earlier than originally planned.
• The Ascend 960PR is expected in Q3 2027, one quarter ahead of schedule.

The Ascend 960DT is set to deliver double the performance of its predecessor, with computing power of 2 PFLOPS (FP8) and 4 PFLOPS (FP4). It will support up to 288GB of memory with a bandwidth of 9.6 TB/s and an interconnect bandwidth of 2.2 TB/s.

System-Level Innovations

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Huawei's announcements extend beyond individual chips, focusing on integrated system-level solutions. The company unveiled the industry's first mass-produced Near-Packaged Optics (NPO) light engine, called Hi-ONE, which is designed to enable high-speed, efficient data transfer between processors.

This NPO technology is a core component of the new Ascend 960 Supercluster, which can scale to 4,096 individual accelerator cards. A single supercluster can provide up to 8 EFLOPS of FP8 computing power and 1 PB of HBM memory capacity. The company also noted that its previous-generation Ascend 910C and 950 superclusters are already seeing significant deployment and commercial use.

Analyst View: A Full-Stack Strategy

CITIC Securities analysts interpret these developments as a strategic shift in China's domestic computing sector from competition over single-chip performance to a full-stack, ecosystem-based approach. This includes hardware, interconnects, storage, and software.

Huawei highlighted improvements to its Lingqu UnifiedBus interconnect protocol, which can now boost the Model Flops Utilization (MFU) of a 100,000-card cluster from 20% to 35%. This efficiency gain is critical for maximizing the performance of large-scale AI training. In the view of CITIC Securities, this holistic strategy is poised to create significant growth opportunities across the entire domestic supply chain, including AI chip design, advanced packaging, and memory manufacturing.